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features ? master and slave operation possible ? supply voltage up to 40v ? operating voltage v s = 5v to 27v ? typically 10 a supply current during sleep mode ? typically 57 a supply current in silent mode ? linear low-drop voltage regulator: ? normal, fail-safe, and silent mode ? ata6622 v cc = 3.3v 2% ? ata6624 v cc = 5.0v 2% ? ATA6626 v cc = 5.0v 2%, txd time-out timer disabled ? in sleep mode v cc is switched off ? vcc- undervoltage detection (4 ms r eset time) and watchdog reset logical combined at open drain output nres ? negative trigger input for watchdog ? boosting the voltage regulator possib le with an external npn transistor ? lin physical layer according to lin 2.0 specification and saej2602-2 ? wake-up capability via lin-bus, wake pin, or kl_15 pin ? inh output to control an extern al voltage regulator or to s witch off the master pull up resistor ? txd time-out timer; ATA6626 txd time-out timer is disabled ? bus pin is overtemperature and short circuit protected versus gnd and battery ? adjustable watchdog time via external resistor ? advanced emc and esd performance ? esd hbm 8 kv at pins lin and vs according to stm5.1 ? package: qfn 5 mm 5 mm with 20 pins 1. description the ata6622 is a fully integrated lin transceiver, which complies with the lin 2.0 and saej2602-2 specifications. it has a low-drop voltage regulator for 3.3v/50 ma output and a window watchdog. the ata6624 has the same functionality as the ata6622; however, it uses a 5v/50 ma regulator. the ATA6626 has the same func- tionality as ata6624 without a txd time-out timer. the voltage regulator is able to source 50 ma up to v s = 18v. the output current of the regulator can be boosted by using an external npn transistor. this chip combination makes it possible to develop inexpensive, simple, yet powerful slave and master nodes for lin-bus systems. ata6622/ata6624/ATA6626 are designed to handle the low-speed data communica- tion in vehicles, e.g., in convenience electronics. improved slope control at the lin-driver ensures secure data communication up to 20 kbaud. sleep mode and silent mode guarantee very low current consumption. the ATA6626 is able to switch the lin unlimited to dominant le vel via txd for low data rates. lin bus transceiver with 3.3v (5v) regulator and watchdog ata6622 ata6624 ATA6626 4986f?auto?07/08
2 4986f?auto?07/08 ata6622/ata6624/ATA6626 figure 1-1. block diagram adjustable watchdog oscillator short circuit and overtemperature protection txd time-out timer edge detection debounce time internal testing unit control unit slew rate control wake-up bus timer mode select undervoltage reset normal/silent/ fail-safe mode 3.3/5v /50 ma/2% rf filter watchdog out 14 1 5 11 rxd gnd ntrig pvcc pvcc pvcc tm mode en txd kl_15 16 wake receiver 9 4 15 13 3 normal and fail-safe mode normal and fail-safe mode 18 19 12 7 20 lin wd_osc nres pvcc vcc vs inh 10 *) * ) not in ATA6626
3 4986f?auto?07/08 ata6622/ata6624/ATA6626 2. pin configuration figure 2-1. pinning qfn20 67 8 10 9 20 19 18 qfn 5 mm 5 mm 0.65 mm pitch 20 lead ata6622/24/26 16 11 12 13 14 15 txd nres wd_osc tm mode kl15 gnd pvcc vcc vs inh rxd gnd lin gnd gnd wake ntrig gnd en 5 4 3 2 1 17 table 2-1. pin description pin symbol function 1 en enables the device in normal mode 2 gnd system ground (optional) 3 ntrig low-level watchdog trigger input from microcontroller 4 wake high-voltage input for local wake-up request; if not needed, connect to vs 5 gnd system ground (mandatory) 6 gnd system ground (optional) 7 lin lin-bus line input/output 8 gnd system ground (optional) 9 rxd receive data output 10 inh battery related output for controlling an external voltage regulator 11 txd transmit data input; active low output (s trong pull down) after a local wake-up request 12 nres output undervoltage and watchdog reset (open drain) 13 wd_osc external resistor for adjustable watchdog timing 14 tm for factory testing only (tie to ground) 15 mode for debug mode: low, watchdog is on; high, watchdog is off 16 kl_15 ignition detection (edge sensitive) 17 gnd system ground (optional) 18 pvcc 3.3v/5v regulator sense input pin 19 vcc 3.3v/5v regulator output/driver pin 20 vs battery supply backside heat slug is connected to all gnd pins
4 4986f?auto?07/08 ata6622/ata6624/ATA6626 3. functional description 3.1 physical layer compatibility since the lin physical layer is independent from hi gher lin layers (e.g., the lin protocol layer), all nodes with a lin physical layer according to re vision 2.0 can be mixed with lin physical layer nodes, which, according to older versions (i.e., lin 1.0, lin 1.1, lin 1.2, lin 1.3), are without any restrictions. 3.2 supply pin (vs) the lin operating voltage is v s = 5v to 27v. an undervoltage detection is implemented to dis- able data transmission if v s falls below vs th < 4v in order to avoid false bus messages. after switching on vs, the ic starts in fail-safe mode, and the voltage regulator is switched on (i.e., 3.3v/5v/50 ma output capability). the supply current is typically 10 a in sleep mode and 57 a in silent mode. 3.3 ground pin (gnd) the ic is neutral on the lin pin in the event of gnd disconnection. it is able to handle a ground shift up to 11.5% of vs. the mandatory system ground is pin 5. 3.4 voltage regulator output pin (vcc) the internal 3.3v/5v voltage regulator is capable of driving loads with up to 50 ma. it is able to supply the microcontroller and other ics on the pcb and is protected against overloads by means of current limitation and overtemperature shut-down. furthermore, the output voltage is monitored and will cause a reset si gnal at the nres output pin if it drops below a defined thresh- old v thun . to boost up the maximum load current, an external npn transistor may be used, with its base connected to the vcc pin and its emitter connected to pvcc. 3.5 voltage regulator sense pin (pvcc) the pvcc is the sense input pin of the 3.3v/5v voltage regulator. for normal applications (i.e., when only using the internal output transistor), this pin is connected to the vcc pin. if an exter- nal boosting transistor is used, the pvcc pin must be connected to the output of this transistor, i.e., its emitter terminal. 3.6 bus pin (lin) a low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor compliant with the lin 2.0 specificat ion are implemented. the allowed voltage range is between ?27v and +40v. reverse currents from the lin bus to vs are suppressed, even in the event of gnd shifts or battery disconnection. lin receiver thresholds are compatible with the lin protocol specification. the fall time from recessive to dominant bus state and the rise time from dominant to recessive bus state are slope controlled.
5 4986f?auto?07/08 ata6622/ata6624/ATA6626 3.7 input/output pin (txd) in normal mode the txd pin is the microcontroller interface used to control the state of the lin output. txd must be pulled to ground in order to have a low lin-bus. if txd is high or uncon- nected (internal pull-up resistor), the lin output transistor is turned off, and the bus is in recessive state. during fail-safe mode, this pin is used as output. it is current-limited to < 8 ma. and is latched to low if the last wake-up event wa s from pin wake or kl_15. 3.8 txd dominant ti me-out function the txd input has an internal pull-up resistor. an internal timer prevents the bus line from being driven permanently in dominant state. if txd is forced to low for longer than t dom > 6 ms, the lin-bus driver is switched to recessive state. nevertheless, when switching to sleep mode, the actual level at the txd pin is relevant. to reactivate the lin bus driver, switch txd to high (> 10 s). the time-out function is disabled in the ATA6626. switching to dominant level on the lin bus occurs without any time limitations. 3.9 output pin (rxd) the output pin reports the state of the lin-bus to the microcontroller. lin high (recessive state) is reported by a high level at rxd; lin low (dominant state) is reported by a low level at rxd. the output has an internal pull-up structure with typically 5 k to vcc. the ac characteristics can be defined with an external load capacitor of 20 pf. the output is short-circuit protected. rxd is switched off in unpowered mode (i.e., v s = 0v). 3.10 enable input pin (en) the enable input pin controls the operation mode of the interface. if en is high, the interface is in normal mode, with transmission paths from txd to lin and from lin to rxd both active. the vcc voltage regulator operates with 3.3v/5v/50 ma output capability. if en is switched to lo w while txd is still high, the device is forced to silent mode. no data trans- mission is then possible, and the current consumption is reduced to i vs typ. 57 a. the vcc regulator has its full functionality. if en is switched to low while txd is low, the device is forced to sleep mode. no data transmis- sion is possible, and the voltage regulator is switched off. 3.11 wake input pin (wake) the wake input pin is a high-voltage input used to wake up the device from sleep mode or silent mode. it is usually connected to an external switch in the application to generate a local wake-up. a pull-up current source, typically 10 a, is implemented. if a local wake-up is not needed for the application, connect the wake pin directly to the vs pin. 3.12 mode input pin (mode) connect the mode pin directly or via an exte rnal resistor to gnd for normal watchdog opera- tion. to debug the software of the connected microcontroller, connect mode pin to 3.3v/5v and the watchdog is switched off.
6 4986f?auto?07/08 ata6622/ata6624/ATA6626 3.13 tm input pin the tm pin is used for final production measurements at atmel ? . in normal application, it has to be always connected to gnd. 3.14 kl_15 pin the kl_15 pin is a high-voltage input used to wake up the device from sleep or silent mode. it is an edge sensitive pin (low-to-high transition). it is usually connected to ignition to generate a local wake-up in the application when the igniti on is switched on. although kl_15 pin is high voltage (v batt ), it is possible to switch the ic into sleep or silent mode. connect the kl_15 pin directly to gnd if you do not need it. a debounce timer with a typical tdb kl_15 of 160 s is implemented. the input voltage threshold can be adjusted by varying the external resistor due to the input cur- rent i kl_15 . to protect this pin against voltage transients, a serial resistor of 50 k and a ceramic capacitor of 100 nf are recommended. with this rc combination you can increase the wake-up time tw kl_15 and, therefore, the sensitivity against transients on the ignition kl.30. you can also increase the wake-up time using external capacitors with higher values. 3.15 inh output pin the inh output pin is used to switch an external voltage regulator on during normal or fail-safe mode. the inh pin is switched off in sleep or silent mode. it is possible to switch off the external 1k master resistor via the inh pin for master node applications. the inh pin is switched off during vcc undervoltage reset. 3.16 reset output pin (nres) the reset output pin, an open drain output, switches to low during v cc undervoltage or a watchdog failure. 3.17 wd_osc output pin the wd_osc output pin provides a typical volta ge of 1.2v, which supplies an external resistor with values between 34 k and 120 k to adjust the watchdog oscillator time. 3.18 ntrig input pin the ntrig input pin is the trig ger input for the window watchdog. a pull-up resistor is imple- mented. a negative edge triggers the watchdog. the trigger signal (low) must exceed a minimum time t trigmin to generate a watchdog trigger. 3.19 wake-up events from sleep or silent mode ?lin-bus ? wake pin ?en pin ? kl_15
7 4986f?auto?07/08 ata6622/ata6624/ATA6626 4. modes of operation figure 4-1. modes of operation 4.1 normal mode this is the normal transmitting and receiving mode. the voltage regulator is in normal mode and can source 50 ma. the undervoltage detection is activated. the watchdog needs a trigger sig- nal from ntrig to avoid resets at nres. if nr es is switched to low, the ic changes state to fail-safe mode. 4.2 silent mode a falling edge at en when txd is high switches the ic into silent mode. the txd signal has to be logic high during the mode select window (see figure 4-2 on page 8 ). the transmission path is disabled in silent mode. the overall supply current from v batt is a combination of the i vssi 57 a plus the vcc regulator output current i vcc . the 3.3v/5v regulator with a 2% tolerance can source up to 50 ma. the internal slave termina- tion between the lin pin and the vs pin is disabled in silent mode to minimize the power dissipation in the event that the lin pin is shor t-circuited to gnd. only a weak pull-up current (typically 10 a) between the lin pin and the vs pin is present. silent mode can be activated independently from the ac tual level on the lin, wake, or kl_15 pins. if an undervoltage condi- tion occurs, the nres is switched to low, and the ic changes its state to fail-safe mode. unpowered mode v batt = 0v a: v s > 5v b: v s < 4v c: bus wake-up event d: wake up from wake or kl_15 pin fail-safe mode normal mode vcc: 3.3v/5v/50 ma with undervoltage monitoring communication: on watchdog : on vcc : 3.3v/5v/50 ma with undervoltage monitoring communication : off watchdog : on silent mode vcc: 3.3v/5v/50 ma with undervoltage monitoring communication: off watchdog : off sleep mode vcc: switched off communication: off watchdog : off go to silent command a txd = 0 en = 0 txd = 1 en = 0 en = 1 en = 1 en = 1 b b b c + d + e e c + d b local wake-up event go to sleep command e: nres switches to low
8 4986f?auto?07/08 ata6622/ata6624/ATA6626 a voltage less than the lin pre_wake detection vlinl at the lin pin activates the internal lin receiver. figure 4-2. switch to silent mode a falling edge at the lin pin followed by a dominant bus level maintained for a certain time period (t bus ) and the following rising edge at the lin pin (see figure 4-3 on page 9 ) result in a remote wake-up request. the device switches from silent mode to fail-safe mode. the internal lin slave termination resistor is switched on. the remote wake-up request is indicated by a low level at the rxd pin to interr upt the microcontroller (see figure 4-3 on page 9 ). en high can be used to switch directly to normal mode. delay time silent mode t d _sleep = maximum 20 s mode select window lin switches directly to recessive mode t d = 3.2 s lin vcc nres txd en normal mode silent mode
9 4986f?auto?07/08 ata6622/ata6624/ATA6626 figure 4-3. lin wake up from silent mode 4.3 sleep mode a falling edge at en when txd is low switches the ic into sleep mode. the txd signal has to be logic low during the mode select window ( figure 4-4 on page 10 ). the transmission path is disabled in sleep mode. the supply current i vssleep from v batt is typically 10 a. the vcc regulator is switched off. nres and rxd are low. the internal slave termination between the lin pin and vs pin is disabled to minimize the power dissipation in the event that the lin pin is short-circuited to gnd. only a w eak pull-up current (typically 10 a) between the lin pin and the vs pin is present. sleep mode can be activated independently from the current level on the lin, wake, or kl_15 pin. a voltage less than the lin pre_wake detection vlinl at the lin pin activates the internal lin receiver. a falling edge at the lin pin followed by a dominant bus level maintained for a certain time period (t bus ) and a rising edge at pin lin respectively result in a remote wake-up request. the device switches from sleep mode to fail-safe mode. watchdog off start watchdog lead time t d watchdog undervoltage detection active silent mode 3.3v/5v/50 ma fail safe mode 3.3v/5v/50 ma normal mode low fail-safe mode normal mode en high node in silent mode high high nres en vcc voltage regulator rxd lin bus bus wake-up filtering time t bus txd
10 4986f?auto?07/08 ata6622/ata6624/ATA6626 the vcc regulator is activated, and the internal lin slave termination resistor is switched on. the remote wake-up request is indicated by a low level at the rxd pin to interrupt the microcon- troller (see figure 4-5 on page 11 ). en high can be used to switch directly from sleep/ silent to fail-safe mode. if en is still high after vcc ramp up and undervoltage reset time, the ic switches to the normal mode. figure 4-4. switch to sleep mode 4.4 fail-safe mode the device automatically switches to fail-safe mode at syst em power-up. the voltage regulator is switched on (vcc = 3.3v/5v/2%/50 ma) (see figure 5-1 on page 14 ). the nres output switches to low for t res = 4 ms and gives a reset to the microcontroller. lin communication is switched off. the ic stays in this mode until en is switched to high. the ic then changes to nor- mal mode. a power down of v batt (v s < 4v) during silent or sleep mode switches the ic into fail-safe mode after power up. a low at nres switches into fail-safe mode directly. during fail-safe mode the txd pin is an output and signals the last wake-up source. 4.5 unpowered mode if you connect battery voltage to the application circuit, the voltage at the vs pin increases according to the block capacitor (see figure 5-1 on page 14 ). after vs is higher than the vs undervoltage threshold vs th , the ic mode changes from unpowered mode to fail-safe mode. the vcc output voltage reaches its nominal value after t vcc . this time, t vcc , depends on the vcc capacitor and the load. the nres is low for the reset time delay t reset . during this time, t reset , no mode change is possible. delay time sleep mode t d_sleep = maximum 20 s lin switches directly to recessive mode t d = 3.2 s lin vcc nres txd en sleep mode normal mode mode select window
11 4986f?auto?07/08 ata6622/ata6624/ATA6626 figure 4-5. lin wake up from sleep mode table 4-1. table of modes mode of operation transceiver vcc watchdog wd_osc inh rxd lin fail-safe off 3.3v/5v on 1.23v on high recessive normal on 3.3v/5v on 1.23v on high txd depending silent off 3.3v/5v off 0v off high recessive sleep off 0v off 0v off 0v recessive regulator wake-up time off state on state low fail-safe mode normal mode en high microcontroller start-up time delay reset time low or floating floating watchdog nres en vcc voltage regulator rxd lin bus bus wake-up filtering time t bus txd watchdog off start watchdog lead time t d
12 4986f?auto?07/08 ata6622/ata6624/ATA6626 5. wake-up scenarios from silent or sleep mode 5.1 remote wake-up via dominant bus state a voltage less than the lin pre_wake detection v linl at the lin pin activates the internal lin receiver. a falling edge at the lin pin followed by a dominant bus level v busdom maintained for a certain time period (t bus ) and a rising edge at pin lin result in a remote wake-up request. the device switches from silent or sleep mode to fail-safe mode. the vcc voltage regulator is/remains activated, the inh pin is switched to high, and the internal slave termination resistor is switched on. the remote wake-up request is indicated by a low level at the rxd pin to generate an inter- rupt for the microcontroller. a low level at the lin pin in the normal mode starts the bus wake-up filtering time, and if the ic is switched to silent or sleep mode , it will receive a wake-up after a positive edge at the lin pin. 5.2 local wake-up via pin wake a falling edge at the wake pin followed by a low level maintained for a certain time period (t wake ) results in a local wake-up request. the device switches to fail-safe mode. the internal slave termination resistor is switched on. the loca l wake-up request is indicated by a low level at the rxd pin to generate an interrupt in the microcontroller and a strong pull down at txd. when the wake pin is low, it is possib le to switch to silent or sleep mode via pin en. in this case, the wake-up signal has to be switch ed to high > 10 s before the negative edge at wake starts a new local wake-up request. 5.3 local wake-up via pin kl_15 a positive edge at pin kl_15 followed by a high voltage level for a certain time period (> t kl_15 ) results in a local wake-up request. the device switches into the fail-safe mode. the internal slave termination resistor is switched on. the ex tra long wake-up time ensures that no transients at kl_15 create a wake up. the local wake-up request is indicated by a low level at the rxd pin to generate an interrupt for the microcontroller and a strong pull down at txd. during high-level voltage at pin kl_15, it is possible to switch to silent or sleep mode via pin en. in this case, the wake-up signal has to be switched to low > 250 s before the positive edge at kl_15 starts a new local wake-up request. with external rc combination, the time is even longer. 5.4 wake-up source recognition the device can distinguish between a local wake-up request (wake or kl_15 pins) and a remote wake-up request (dominant lin bus state). the wake-up source can be read on the txd pin in fail-safe mode. a high level indicates a remote wake-up request (weak pull up at the txd pin); a low level indicates a local wake-up request (strong pull down at the txd pin). the wake-up request flag (signalled on the rxd pin), as well as the wake-up source flag (signalled on the txd pin), is immediately reset if the microcontroller sets the en pin to high (see figure 4-2 on page 8 and figure 4-3 on page 9 ) and the ic is in normal mode. the last wake-up source flag is stored and signalled in fail-safe mode at the txd pin.
13 4986f?auto?07/08 ata6622/ata6624/ATA6626 5.5 fail-safe features ? during a short-circuit at lin to v battery , the output limits the output current to i bus_lim . due to the power dissipation, the chip temperature exceeds t linoff , and the lin output is switched off. the chip cools down and after a hysteresis of t hys , switches the output on again. rxd stays on high because lin is high. during lin overtemperature switch-off, the vcc regulator works independently. ? during a short-circuit from lin to gnd the ic can be switched into sleep or silent mode. if the short-circuit disappears, the ic starts with a remote wake-up. ? the reverse current is very low < 15 a at the lin pin during loss of v batt or gnd. this is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. ? during a short circuit at vcc, the output limits the output current to i vccn . because of undervoltage, nres switches to low and sends a reset to the microcontroller. the ic switches into fail-safe mode. if the chip temperature exceeds the value t vccoff , the vcc output switches off. the chip cools down and after a hysteresis of t hys , switches the output on again. because of the fail-safe mode, the vcc voltage will switch on again although en is switched off from the microcontroller. the microcontroller can start with its normal operation. ? en pin provides a pull-down resistor to force the transceiver into recessive mode if en is disconnected. ? rxd pin is set floating if v batt is disconnected. ? txd pin provides a pull-up resistor to force the transceiver into recessive mode if txd is disconnected. ? if txd is short-circuited to gnd, it is possi ble to switch to sleep mode via enable after t dom > 20 ms (only for ata6622/ata6624). ? if the wd_osc pin has a short-circuit to gnd or the resistor is disconnected, the watchdog runs with an internal oscillator and guarantees a reset after th e second ntrig signal at the latest. 5.6 voltage regulator the voltage regulator needs an external capacitor for compensation and for smoothing the dis- turbances from the microcontroller. it is reco mmended to use an electrolythic capacitor with c > 10 f and a ceramic capacitor with c = 100 nf. the values of these capacitors can be var- ied by the customer, depending on the application. the main power dissipation of the ic is created from the vcc output current i vcc , which is needed for the application. in figure 5-2 on page 14 the safe operating area of the ata6622/ata6624/ATA6626 is shown.
14 4986f?auto?07/08 ata6622/ata6624/ATA6626 figure 5-1. vcc voltage regulator: ramp-up and undervoltage detection figure 5-2. power dissipation: safe operating area versus vcc output current and supply voltage v s at different ambient temperatures due to r thja = 35 k/w for programming purposes of the microcontroller it is potentially necessary to supply the v cc output via an external power supply while the v s pin of the system basis chip is disconnected. this behavior is no problem for the system basis chip. nres 5v/3.3v t t t vs 5v/3.3v v thun t res_f t reset t vcc 5.5v/3.8v 12v 0 10 20 30 40 50 60 35791113151719 v s /v i vcc /ma t amb = 125?c t amb = 105?c
15 4986f?auto?07/08 ata6622/ata6624/ATA6626 6. watchdog the watchdog anticipates a trigger signal from the microcontroller at the ntrig (negative edge) input within a time window of t wd . the trigger signal must exceed a minimum time t trigmin > 200 ns. if a triggering signal is not received, a reset signal will be generated at output nres. the timing basis of the watchdog is provided by the internal oscillator. its time period, t osc , is adjustable via the external resistor r wd_osc (34 k to 120 k ). during silent or sleep mode the watchdog is switched off to reduce current consumption. the minimum time for the first watchdog pulse is required after the undervoltage reset at nres disappears. it is defined as lead time t d . after wake up from sleep or silent mode, the lead time t d starts with the negative edge of the rxd output. 6.1 typical timing sequence with r wd_osc = 51 k the trigger signal t wd is adjustable between 20 ms and 64 ms using the external resistor r wd_osc . for example, with an external resistor of r wd_osc = 51 k 1%, the typical parameters of the watchdog are as follows: t osc = 0.405 r wd_osc ? 0.0004 (r wd_osc ) 2 (r wd_osc in k ; t osc in s) t osc = 19.6 s due to 51 k t d = 7895 19.6 s = 155 ms t 1 = 1053 19.6 s = 20.6 ms t 2 = 1105 19.6 s = 21.6 ms t nres = constant = 4 ms after ramping up the battery voltage, the 3.3v/5v regulator is switched on. the reset output nres stays low for the time t reset (typically 4 ms), then it switches to high, and the watchdog waits for the trigger sequence from the microcontroller. the lead time, t d , follows the reset and is t d = 155 ms. in this time, the first watchdog pulse from the microcontroller is required. if the trig- ger pulse ntrig occurs during this time, the time t 1 starts immediately. if no trigger signal occurs during the time t d , a watchdog reset with t nres = 4 ms will reset the microcontroller after t d = 155 ms. the times t 1 and t 2 have a fixed relationship between each other. a triggering signal from the microcontroller is anticipated within the time frame of t 2 = 21.6 ms. to avoid false trig- gering from glitches, the trigger pulse must be longer than t trig,min > 200 ns. this slope serves to restart the watchdog sequence. if the trigge ring signal fails in this open window t 2 , the nres output will be drawn to ground. a triggering signal during the closed window t 1 immediately switches nres to low.
16 4986f?auto?07/08 ata6622/ata6624/ATA6626 figure 6-1. timing sequence with r wd_osc = 51 k 6.2 worst case calculation with r wd_osc = 51 k the internal oscillator has a tolerance of 20%. this means that t 1 and t 2 can also vary by 20%. the worst case calculation for the watchdog period t wd is calculated as follows. the ideal watchdog time t wd is between the maximum t 1 and the minimum t 1 plus the minimum t 2 . t 1,min = 0.8 t 1 = 16.5 ms, t 1,max = 1.2 t 1 = 24.8 ms t 2,min = 0.8 t 2 = 17.3 ms, t 2,max = 1.2 t 2 = 26 ms t wdmax = t 1min + t 2min = 16.5 ms + 17.3 ms = 33.8 ms t wdmin = t 1max = 24.8 ms t wd = 29.3 ms 4.5 ms (15%) a microcontroller with an oscillator tolerance of 15% is sufficient to supply the trigger inputs correctly. t nres = 4 ms undervoltage reset watchdog reset t reset = 4 ms t trig > 200 ns t 1 = 20.6 ms t 2 = 21 ms t 2 t 1 t wd t d = 155 ms vcc 3.3v/5v ntrig nres table 6-1. typical watchdog timings r wd_osc k oscillator period t osc /s lead time t d /ms closed window t 1 /ms open window t 2 /ms trigger period from microcontroller t wd /ms reset time t nres /ms 34 13.3 105 14.0 14.7 19.9 4 51 19.61 154.8 20.64 21.67 29.32 4 91 33.54 264.80 35.32 37.06 50.14 4 120 42.84 338.22 45.11 47.34 64.05 4
17 4986f?auto?07/08 ata6622/ata6624/ATA6626 7. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit supply voltage v s v s ?0.3 +40 v pulse time 500 ms t a = 25c output current i vcc 50 ma v s +40 v pulse time 2min t a = 25c output current i vcc 50 ma v s 27 v wake (with 33 k serial resistor) kl_15 (with 50 k /100 nf) dc voltage transient voltage due to iso7637 (coupling 1 nf) ?1 ?150 +40 +100 v v inh - dc voltage ?0.3 +40 v lin - dc voltage ?27 +40 v logic pins (rxd, txd, en, nres, ntrig, wd_osc, mode, tm) ?0.3 +5.5 v output current nres i nres +2 ma pvcc dc voltage vcc dc voltage ?0.3 ?0.3 +5.5 +6.5 v v according to ibee lin emc test spec. 1.0 following iec 61000-4-2 - pin vs, lin to gnd - pin wake (33 k serial resistor) to gnd 6 5 kv kv hbm esd ansi/esd-stm5.1 jesd22-a114 aec-q100 (002) 3 kv cdm esd stm 5.3.1 750 v esd hbm following stm5.1 with 1.5 k 150 pf - pin vs, lin, wake to gnd 8 kv junction temperature t j ?40 +150 c storage temperature t s ?55 +150 c thermal resistance junc tion to heat slug r thjc 10 k/w thermal resistance junction to ambient, where heat slug is soldered to pcb r thja 35 k/w thermal shutdown of vcc regulator 150 165 170 c thermal shutdown of lin output 150 165 170 c thermal shutdown hysteresis 10 c
18 4986f?auto?07/08 ata6622/ata6624/ATA6626 8. electrical characteristics 5v < v s < 27v, -40c < tj < 150c, unless otherwis e specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* 1 vs pin 1.1 nominal dc voltage range vs v s 527va 1.2 supply current in sleep mode sleep mode v lin > v s ? 0.5v v s < 14v (t j = 25c) vs i vssleep 31014aa sleep mode v lin > v st ? 0.5v v s < 14v (t j = 125c) i vssleep 51116aa 1.3 supply current in silent mode bus recessive v s < 14v (t j = 25c) without load at vcc i vssi 47 57 67 a a bus recessive v s < 14v (t j = 125c) without load at vcc i vssi 56 66 76 a a 1.4 supply current in normal mode bus recessive v s < 14v without load at vcc vs i vsrec 0.3 0.8 ma a 1.5 supply current in normal mode bus dominant v s < 14v v cc load current 50 ma vs i vsdom 50 53 ma a 1.6 supply current in fail-safe mode bus recessive v s < 14v without load at vcc vs i vsfail 0.35 0.53 ma a 1.7 v s undervoltage threshold vs v sth 4.0 4.5 5 v a 1.8 vs undervoltage threshold hysteresis vs v sth_hys 0.2 v a 2 rxd output pin 2.1 low-level input current normal mode v lin =0v v rxd =0.4v rxd i rxd 1.3 2.5 8 ma a 2.2 low-level output voltage i rxd = 1 ma rxd v rxdl 0.4 v a 2.3 internal 5 k resistor to v cc rxd r rxd 357k a 3 txd input/output pin 3.1 low-level voltage input txd v txdl ?0.3 +0.8 v a 3.2 high-level voltage input txd v txdh 2 v cc + 0.3v va 3.3 pull-up resistor v txd =0v txd r txd 125 250 400 k a 3.4 high-level leakage current v txd =vcc txd i txd ?3 +3 a a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
19 4986f?auto?07/08 ata6622/ata6624/ATA6626 3.5 low-level input current at local wake-up request fail-safe mode v lin = v s v wake = 0v v txd = 0.4v txd i txdwake 22.58maa 4en input pin 4.1 low-level voltage input en v enl ?0.3 +0.8 v a 4.2 high-level voltage input en v enh 2 v cc + 0.3v va 4.3 pull-down resistor v en = v cc en r en 50 125 200 k a 4.4 low-level input current v en = 0v en i en ?3 +3 a a 5 ntrig watchdog input pin 5.1 low-level voltage input v ntrigl ?0.3 +0.8 v a 5.2 high-level voltage input v ntrigh 2 v cc + 0.3v va 5.3 pull-up resistor v ntrig = 0v r ntrig 125 250 400 k a 5.4 high-level leakage current v ntrig = v cc i ntrig ?3 +3 a a 6 mode input pin 6.1 low-level voltage input v model ?0.3 +0.8 v a 6.2 high-level voltage input v modeh 2 v cc + 0.3v va 6.3 high-level leakage current v mode = v cc or v mode = 0v i mode ?3 +3 a a 7 inh output pin 7.1 high-level voltage i inh = ?15 ma v inhh v s ? 0.8 v s va 7.2 switch-on resistance between vs and inh r inh 30 50 a 7.3 high-level leakage current sleep mode v inh = 27v, v s = 27v i inhl ?3 +3 a a 8 lin bus driver: bus load conditions: load 1 (small): 1 nf, 1 k ; load 2 (large): 10 nf, 500 ; internal pull-up r rxd = 5 k ; c rxd = 20 pf 10.5, 10.6 and 10.7 specifies the timing parameters for proper operation at 20 kbps 8.1 driver recessive output voltage load1/load2 lin v busrec 0.9 v s v s va 8.2 driver dominant voltage v vs = 7v r load = 500 lin v _losup 1.2 v a 8.3 driver dominant voltage v vs = 18v r load = 500 lin v _hisup 2va 8.4 driver dominant voltage v vs = 7.0v r load = 1000 lin v _losup_1k 0.6 v a 8.5 driver dominant voltage v vs = 18v r load = 1000 lin v _hisup_1k 0.8 v a 8.6 pull-up resistor to v s the serial diode is mandatory lin r lin 20 30 60 k a 8. electrical characteristics (continued) 5v < v s < 27v, -40c < tj < 150c, unless otherwis e specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
20 4986f?auto?07/08 ata6622/ata6624/ATA6626 8.7 lin current limitation v bus = v batt_max lin i bus_lim 40 120 200 ma a 8.8 input leakage current at the receiver including pull-up resistor as specified input leakage current driver off v bus = 0v v batt = 12v lin i bus_pas_dom ?1 ?0.35 ma a 8.9 leakage current lin recessive driver off 8v < v batt < 18v 8v < v bus < 18v v bus v batt lin i bus_pas_rec 15 20 a a 8.10 leakage current when control unit disconnected from ground. loss of local ground must not affect communication in the residual network. gnd device = v s v batt = 12v 0v < v bus < 18v lin i bus_no_gnd ?10 +0.5 +10 a a 8.11 node has to sustain the current that can flow under this condition. bus must remain operational under this condition. v batt disconnected v sup_device = gnd 0v < v bus < 18v lin i bus 515aa 9 lin bus receiver 9.1 center of receiver threshold v bus_cnt = (v th_dom + v th _ rec )/2 lin v bus_cnt 0.475 v s 0.5 v s 0.525 v s va 9.2 receiver dominant state v en = 5v lin v busdom 0.4 v s va 9.3 receiver recessive state v en = 5v lin v busrec 0.6 v s va 9.4 receiver input hysteresis v hys = v th_rec ? v th_dom lin v bushys 0.028 v s 0.1 v s 0.175 v s va 9.5 pre_wake detection lin high-level input voltage lin v linh v s ? 1v v s + 0.3v va 9.6 pre_wake detection lin low-level input voltage activates the lin receiver lin v linl ?27 v s ? 3.3v va 10 internal timers 10.1 dominant time for wake-up via lin bus v lin = 0v t bus 30 90 150 s a 10.2 time delay for mode change from fail-safe into normal mode via en pin v en = 5v t norm 51520sa 10.3 time delay for mode change from normal mode to sleep mode via en pin v en = 0v t sleep 2 7 12 s a 10.4 txd dominant time-out timer (ATA6626 disabled) v txd = 0v t dom 61320msa 8. electrical characteristics (continued) 5v < v s < 27v, -40c < tj < 150c, unless otherwis e specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
21 4986f?auto?07/08 ata6622/ata6624/ATA6626 10.5 time delay for mode change from silent mode into normal mode via en v en = 5v t s_n 51540sa 10.6 duty cycle 1 th rec(max) = 0.744 v s th dom(max) = 0.581 v s v s = 7.0v to 18v t bit = 50 s d1 = t bus_rec(min) /(2 t bit ) d1 0.396 a 10.7 duty cycle 2 th rec(min) = 0.422 v s th dom(min) = 0.284 v s v s = 7.6v to 18v t bit = 50 s d2 = t bus_rec(max) /(2 t bit ) d2 0.581 a 10.8 duty cycle 3 th rec(max) = 0.778 v s th dom(max) = 0.616 v s v s = 7.0v to 18v t bit = 96 s d3 = t bus_rec(min) /(2 t bit ) d3 0.417 a 10.9 duty cycle 4 th rec(min) = 0.389 v s th dom(min) = 0.251 v s v s = 7.6v to 18v t bit = 96 s d4 = t bus_rec(max) /(2 t bit ) d4 0.590 a 10.10 slope time falling and rising edge at lin v s = 7.0v to 18v slope time dominant and recessive edges t slope_fall t slope_rise 3.5 22.5 s a 11 receiver electrical ac parameters of the lin physical layer lin receiver, rxd load conditions: internal pull-up r rxd = 5 k ; c rxd = 20 pf 11.1 propagation delay of receiver ( figure 8-1 on page 24 ) v s = 7.0v to 18v t rx_pd = max(t rx_pdr , t rx_pdf ) t rx_pd 6sa 11.2 symmetry of receiver propagation delay rising edge minus falling edge v s = 7.0v to 18v t rx_sym = t rx_pdr ? t rx_pdf t rx_sym ?2 +2 s a 12 nres open drain output pin 12.1 low-level output voltage v s 5.5v i nres = 1 ma i nres = 250 a v nresl 0.2 0.14 v v a 12.2 low-level output low 10 k to v cc v cc = 0v v nresll 0.2 v a 12.3 undervoltage reset time v vs 5.5v c nres = 20 pf t reset 246msa 12.4 reset debounce time for falling edge v vs 5.5v c nres = 20 pf t res_f 1.5 10 s a 8. electrical characteristics (continued) 5v < v s < 27v, -40c < tj < 150c, unless otherwis e specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
22 4986f?auto?07/08 ata6622/ata6624/ATA6626 13 watchdog oscillator 13.1 voltage at wd_osc in normal mode i wd_osc = ?200 a v vs 4v v wd_osc 1.13 1.23 1.33 v a 13.2 positive values of resistor r osc 34 120 k a 13.3 oscillator period r osc = 34 k t osc 10.65 13.3 15.97 s a 13.4 oscillator period r osc = 51 k t osc 15.68 19.6 23.52 s a 13.5 oscillator period r osc = 91 k t osc 26.83 33.5 40.24 s a 13.6 oscillator period r osc = 120 k t osc 34.2 42.8 51.4 s a 14 watchdog timing relative to t osc 14.1 watchdog lead time after reset t d 7895 cycles a 14.2 watchdog closed window t 1 1053 cycles a 14.3 watchdog open window t 2 1105 cycles a 14.4 watchdog reset time nres t nres 3.244.8msa 15 kl_15 pin 15.1 high-level input voltage r v = 50 k positive edge initializes a wake-up v kl_15h 4 v s + 0.3v va 15.2 low-level input voltage r v = 50 k v kl_15l ?1 +2 v a 15.3 kl_15 pull-down current v s < 27v v kl_15 = 27v i kl_15 50 60 a a 15.4 internal debounce time without external capacitor tdb kl_15 80 160 250 s a 15.5 kl_15 wake-up time (r v = 50 k , c = 100 nf) r v = 50 k , c = 100 nf tw kl_15 0.424.5msc 16 wake pin 16.1 high-level input voltage v wakeh v s ? 1v v s + 0.3v va 16.2 low-level input voltage initializes a wake-up signal v wakel ?1 v s ? 3.3v va 16.3 wake pull-up current v s < 27v v wake = 0v i wake ?30 ?10 a a 16.4 high-level leakage current v s = 27v v wake = 27v i wakel ?5 +5 a a 16.5 time of low pulse for wake-up via wake pin v wake = 0v i wakel 30 70 150 s a 8. electrical characteristics (continued) 5v < v s < 27v, -40c < tj < 150c, unless otherwis e specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
23 4986f?auto?07/08 ata6622/ata6624/ATA6626 17 vcc voltage regulator ata6622 17.1 output voltage vcc 4v < v s < 18v (0 ma to 50 ma) vcc nor 3.234 3.366 v a 17.2 output voltage vcc at low vs 3v < v s < 4v vcc low v s ? v drop 3.366 v a 17.3 regulator drop voltage v s > 3v i vcc = ?15 ma v drop1 200 mv a 17.4 regulator drop voltage v s > 3v i vcc = ?50 ma v drop2 500 700 mv a 17.5 line regulation 4v < v s < 18v vcc line 1%a 17.6 load regulation 5 ma < i vcc < 50 ma vcc load 0.5 2 % a 17.7 power supply ripple rejection 10 hz to 100 khz c vcc = 10 f v s = 14v, i vcc = ?15 ma 50 db a 17.8 output current limitation v s > 4v i vccs ?200 ?160 ma a 17.9 load capacity 1 < esr < 5 @ 100 khz c load 1.8 10 f d 17.10 vcc undervoltage threshold referred to vcc v s > 4v v thunn 2.8 3.2 v a 17.11 hysteresis of undervoltage threshold referred to vcc v s > 4v vhys thun 150 mv a 17.12 ramp-up time v s > 4v to v cc = 3.3v c vcc = 2.2 f i load = ?5 ma at vcc t vcc 100 250 s a 18 vcc voltage regulator ata6624/ATA6626 18.1 output voltage vcc 5.5v < v s < 18v (0 ma to 50 ma) vcc nor 4.9 5.1 v a 18.2 output voltage vcc at low vs 4v < v s < 5.5v vcc low v s ? v d 5.1 v a 18.3 regulator drop voltage v s > 4v i vcc = ?20 ma v d1 250 mv a 18.4 regulator drop voltage v s > 4v i vcc = ?50 ma v d2 400 600 mv a 18.5 regulator drop voltage v s > 3.3v i vcc = ?15 ma v d3 200 mv a 18.6 line regulation 5.5v < v s < 18v vcc line 1%a 18.7 load regulation 5ma < i vcc < 50 ma 100 khz vcc load 0.5 2 % a 18.8 output current limitation v s > 5.5v i vccs ?200 ?130 ma a 18.9 load capacity 1 < esr < 5 v thunn 1.8 10 f d 18.10 vcc undervoltage threshold referred to vcc v s > 5.5v v thunn 4.2 4.8 v a 18.11 hysteresis of undervoltage threshold referred to vcc v s > 5.5v vhys thun 250 mv a 18.12 ramp-up time v s > 5.5v to v cc = 5v c vcc = 2.2 f i load = ?5 ma at vcc t vcc 130 300 s a 8. electrical characteristics (continued) 5v < v s < 27v, -40c < tj < 150c, unless otherwis e specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
24 4986f?auto?07/08 ata6622/ata6624/ATA6626 figure 8-1. definition of bus timing characteristics txd (input to transmitting node) vs (transceiver supply of transmitting node) rxd (output of receiving node1) rxd (output of receiving node2) lin bus signal thresholds of receiving node1 thresholds of receiving node2 t bus_rec(max) t rx_pdr(1) t rx_pdf(2) t rx_pdr(2) t rx_pdf(1) t bus_dom(min) t bus_dom(max) th rec(max) th dom(max) th rec(min) th dom(min) t bus_rec(min) t bit t bit t bit
25 4986f?auto?07/08 ata6622/ata6624/ATA6626 figure 8-2. application circuit 67 8 10 9 20 19 18 mlp 5 mm 5 mm 0.65 mm pitch 20 lead ata6622/24/26 16 11 12 13 14 15 txd nres lin sub bus wd_osc tm mode master node pull-up debug kl_15 pvcc vcc vs rxd lin gnd wake wake switch 51 k 10 k 1 k 33 k 10 k 47 k 10 k ntrig ntrig microcontroller reset txd rxd en v cc kl15 inh ignition kl30 v battery en 5 4 3 2 1 17 220 pf 100 nf 22 f + 100 nf 10 f 100 nf +
26 4986f?auto?07/08 ata6622/ata6624/ATA6626 figure 8-3. application circuit with external npn 67 8 10 9 20 19 18 mlp 5 mm 5 mm 0.65 mm pitch 20 lead ata6622/24/26 16 11 12 13 14 15 txd nres lin sub bus wd_osc tm mode master node pull-up debug kl_15 pvcc vcc vs rxd lin gnd wake wake switch 51 k 10 k 1 k 33 k 10 k 47 k 10 k ntrig ntrig microcontroller reset txd rxd en v cc kl15 inh ignition kl30 v battery en 5 4 3 2 1 17 220 pf 100 nf 22 f + 100 nf 10 f 100 nf + + 2.2 f 3.3 mjd31c
27 4986f?auto?07/08 ata6622/ata6624/ATA6626 10. package information 9. ordering information extended type number package remarks ata6622-pgpw qfn20 3.3v lin system-basis-c hip, pb-free, 1.5k, taped and reeled ata6624-pgpw qfn20 5v lin system-basis-chi p, pb-free, 1.5k, taped and reeled ata6622-pgqw qfn20 3.3v lin sy stem-basis-chip, pb-fre e, 6k, taped and reeled ata6624-pgqw qfn20 5v lin system-basis-c hip, pb-free, 6k, taped and reeled ATA6626-pgqw qfn20 5v lin system-basis-c hip, pb-free, 6k, taped and reeled specifications according to din technical drawings issue: 2; 09.02.07 drawing-no.: 6.543-5129.01-4 0.2 0.9 0.1 0.65 nom. 16 20 10 6 11 15 5 1 3.1 0.15 bottom 2.6 20 1 5 5 top pin 1 identification package: vqfn_5 x 5_20l exposed pad 3.1 x 3.1 dimensions in mm not indicated tolerances 0.05 0.6 0.1 0.28 0.07 0.05 -0.05 0
28 4986f?auto?07/08 ata6622/ata6624/ATA6626 11. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4986f-auto-05/08 ? section 3.15 ?inh output pin? on page 6 changed ? section 5.5 ?fail-safe features? on page 13 changed ? section 6.1 ?typical timing sequence with r wd_osc = 51 k ? on page 15 changed ? section 8 ?electrical characteristi cs? numbers 1.6 to 1.8 on page 18 changed 4986e-auto-02/08 ? figure 2-1 on page 3 renamed ? figure 6-1 ?timing sequence with r wd_osc = 51 k ? on page 16 changed ? figure 8-3 ?application circuit with ex ternal npn? on page 26 added 4986d-auto-10/07 ? section 9 ?ordering information? on page 26 changed 4986c-auto-09/07 ? features changed ? sections 4.2, 4.3, 4.4 and 4.5 changed ? figures 4-2, 4-3, 4-4, 5-1, 5- 2, 5-3, 5-6, 6-1 and 6-2 changed ? section 7 ?absolute maximum ratings? changed? ? section 8 ?electrical characterist ics?: numbers 17.9 and 18.9 changed 4986b-auto-06/07 ? put datasheet into a new template ? part number ATA6626 added ? features changed ? description text changed ? figure 1-1 ?block diagram? changed ? figure 2-1 ?pinning so8 changed? ? figure 4-3 ?lin wake up from silent mode? changed ? figure 4-5 ?lin wake up from sleep mode? changed ? sections 3.2, 3.4, 3.7, 3.8, 3.9, 3.10, 3.11, 3.12, 3.13 and 3.14 changed ? sections 4.2, 4.3, 4.4, 4.5, 5.1, 5.2, 5.3, 5. 5, 5.6, 6.1 and 6.2 changed ? section 8 ?electrical characteristics?: numbers 1.3, 3.5, 8.4, 12.1, 15.5, 17.9, 18 and 18.9 changed ? figure 8-2 ?application circuit? changed ? section 9 ?ordering information? changed ? section 10 ?package information? changed
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